{"id":39,"date":"2020-04-09T08:45:07","date_gmt":"2020-04-09T08:45:07","guid":{"rendered":"http:\/\/kioswebsvr1.koios.ucy.ac.cy\/mmichael\/?page_id=39"},"modified":"2024-05-19T20:06:42","modified_gmt":"2024-05-19T20:06:42","slug":"publications","status":"publish","type":"page","link":"https:\/\/www.kios.ucy.ac.cy\/mmichael\/index.php\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"\n<p><strong>Book Chapters:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><em>S. Falas<\/em>, C. Konstantinou, and <strong>M. K. Michael<\/strong> (2020), \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/doi.org\/10.1007\/978-3-030-53273-4_8\" target=\"_blank\">Hardware-Enabled Secure Firmware Updates in Embedded Systems<\/a>\u201d. In Metzler C., Gaillardon PE., De Micheli G., Silva-Cardenas C., Reis R. (eds) VLSI-SoC: New Technology Enabler (pp 165-185). VLSI-SoC 2019. IFIP Advances in Information and Communication Technology, vol 586. Springer, Cham.<\/li>\n\n\n\n<li><em>M. Skitsas<\/em>, Marco Restifo, <strong>M. K. Michael<\/strong>, C. Nicopoulos, P. Bernardi, E. Sanchez (2018), \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/digital-library.theiet.org\/content\/books\/10.1049\/pbpc022e_ch15\" target=\"_blank\">Self Testing of Multicore Processors<\/a>\u201d, in Bashir Al-Hashimi and Geoff Merrett (Ed.), <em>Many Core Computing: Hardware and Software<\/em> (pp. 1-30), June 2019, The Institution of Engineering and Technology (IET), e-ISBN: 9781785615832, Chapter DOI: 10.1049\/PBPC022E_ch<\/li>\n\n\n\n<li>C. Bolchini, <strong>M. K. Michael<\/strong>, A. Miele, S. Neophytou (2017) \u201c<a href=\"https:\/\/link.springer.com\/chapter\/10.1007\/978-3-319-54422-9_2\" target=\"_blank\" rel=\"noreferrer noopener\">Dependability Threats<\/a>\u201d, in M. Ottavi, S. Pontarelli, D. Gizopoulos (Ed.), <em>Dependable Multicore Architectures at Nanoscale<\/em> (pp. 1-35), 1st Ed., July 2017, Springer, ISBN-13: 9783319544212.<\/li>\n<\/ul>\n\n\n\n<p><strong>Refereed Archival Journal Articles:<\/strong><\/p>\n\n\n\n<div class=\"wp-block-group\"><div class=\"wp-block-group__inner-container is-layout-flow wp-block-group-is-layout-flow\">\n<ul class=\"wp-block-list\">\n<li><em>A. Kouloumpris, <\/em>G. L. Stavrinides, <strong>M. K. Michael<\/strong>, T. Theocharides, \u201c<a href=\"https:\/\/www.sciencedirect.com\/science\/article\/pii\/S0167739X24000505\" target=\"_blank\" rel=\"noreferrer noopener\">An optimization framework for task allocation in the edge\/hub\/cloud paradigm<\/a>\u201d, <em>Journal in Future Generation Computer Systems (FGCS)<\/em>, Feb 2024, pp. 1-13.<\/li>\n\n\n\n<li><em>M. F. Elrawy<\/em>, C. Fioravanti, G. Oliva, <strong>M. K. Michael<\/strong>, R. Setola, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/10418934\" target=\"_blank\" rel=\"noreferrer noopener\">A Geometrical Approach to Enhance Security Against Cyber Attacks in Digital Substations<\/a>\u201d, <em>IEEE Access<\/em>, Jan 2024, pp. 1-15.<\/li>\n\n\n\n<li><em>M. F. Elrawy<\/em>, L. Hadjidemetriou, C. Laoudias and <strong>M. K. Michael<\/strong>, \u201c<a href=\"https:\/\/www.sciencedirect.com\/science\/article\/pii\/S2352467723001753\" target=\"_blank\" rel=\"noreferrer noopener\">Detecting and Classifying Man-in-the-middle Attacks in the Private Area Network of Smart Grids<\/a>\u201d, <em>Journal of Sustainable Energy, Grids and Networks (SEGAN)<\/em>, Vol. 36, Dec 2023, pp. 1-14.<\/li>\n\n\n\n<li><em>S. Falas, C. Konstantinou, and <\/em><strong><em>M. K. Michael<\/em><\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/dl.acm.org\/doi\/10.1145\/3460234\" target=\"_blank\">A Modular End-to-End Framework for Secure Firmware Updates on Embedded Systems<\/a>\u201d, <em>ACM Journal on Emerging Technologies in Computing Systems (JETC)<\/em>, Vol. 18, No. 1, Jan 2022, pp. 1-19.<\/li>\n\n\n\n<li><em>G. Tertytchny, N. Nicolaou,<\/em><strong><em> M. K. Michael<\/em><\/strong>, \u201c<a href=\"https:\/\/www.sciencedirect.com\/science\/article\/abs\/pii\/S014193312030288X\" target=\"_blank\" rel=\"noreferrer noopener\">Classifying network abnormalities into faults and attacks in IoT-based cyber physical systems using machine learning<\/a>\u201d, <em>Journal of Microprocessors and Microsystems (MICPRO)<\/em>, Elsevier, Vol. 77, Sept 2020, pp. 1-15.<\/li>\n\n\n\n<li><em>S. Hadjitheophanous, <\/em>S. Neophytou, <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/8886719\" target=\"_blank\">Maintaining Scalability of Test Generation using Multicore Shared Memory System<\/a>\u201d,<em> IEEE Transactions <\/em>on VLSI, Vol. 28, No. 2, February 2020, pp. 553- 564.<\/li>\n\n\n\n<li><em>S. Hadjitheophanous,<\/em> S. Neophytou, <strong>M. K. Michael<\/strong>, &#8220;<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8410458\">Exploiting Shared-Memory to Steer Scalability of Fault Simulation using Multicore Systems<\/a>&#8220;,&nbsp;<em>IEEE Transaction on Computer-Aided Design<\/em>, Vol. 38, No. 8, August 2019, pp. 1466-1479.<\/li>\n\n\n\n<li><em>S. Neophytou,<\/em> <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/link.springer.com\/article\/10.1007\/s10836-018-5761-6\" target=\"_blank\">Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering<\/a>\u201d,<em> Journal of Electronic Testing: Theory and Applications (JETTA)<\/em>, Vol. 34, No. 6, December 2018, pp. 667-683.<\/li>\n\n\n\n<li><em>M. Skitsas, C<\/em>. Nicopoulos, <strong>M. K. Michael<\/strong>, &#8220;<a rel=\"noreferrer noopener\" href=\"https:\/\/www.springerprofessional.de\/exploring-system-availability-during-software-based-self-testing\/15418966\" target=\"_blank\">Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs<\/a>&#8220;,&nbsp;<em>Journal of Electronic Testing (JETTA)<\/em>, Vol. 34, No. 1, February 2018, pp. 67-81.<\/li>\n\n\n\n<li><em>M. Skitsas, <\/em>C. Nicopoulos and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/7140775\" target=\"_blank\">DaemonGuard: Enabling O\/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-\/Many-Core Microprocessors<\/a>\u201d,&nbsp;<em>IEEE Transactions on Computers<\/em>, Vol. 65, No. 5, September 2016, pp. 1453-1466.<\/li>\n\n\n\n<li><em>M. Maniatakos, <\/em><strong>M. K. Michael<\/strong> and Y. Makris, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=6953332\" target=\"_blank\">Multiple-Bit Upset Protection in Microprocessor Memory Arrays using Vulnerability-based Parity Optimization and Interleaving<\/a>\u201d,&nbsp;<em>IEEE Transactions on Very Large Scale Integration<\/em>, Vol. 23, No. 11, November 2015, pp. 2447-2460.<\/li>\n\n\n\n<li>H. Kim, S. B. Boga, A. Vitkovskiy,&nbsp;S. Hadjitheophanous, P. V. Gratz, V. Soteriou and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/dl.acm.org\/doi\/10.1145\/2770873\" target=\"_blank\">Use it or Lose it: Proactive, Deterministic Longevity in Future Chip Multiprocessors<\/a>\u201d,&nbsp;<em>ACM Transactions on Design Automation of Electronic Systems, Vol. 20, No. 4, September 2015<\/em>, pp. 1-26.<\/li>\n\n\n\n<li>M. Maniatakos, <strong>M. K. Michael<\/strong>, C. Tirumurti and Y. Makris<em>, <\/em>&#8220;<a rel=\"noreferrer noopener\" href=\"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=6967809\" target=\"_blank\">Revisiting Vulnerability Analysis in Modern Microprocessors<\/a>&#8220;,<em>&nbsp;IEEE Transactions on Computers<\/em>,&nbsp;Vol. 64, No. 9,September 2015, pp. 2664-2674.<\/li>\n\n\n\n<li>M. Ottavi, S. Pontarelli, D. Gizopoulos, C. Bolchini, <strong>M. K. Michael<\/strong>, L. Anghel, M. Tahoori, A. Paschalis, P. Reviriego, O. Bringmann, V. Izosimov, H. Manhaeve, C. Strydis, S. Hamdioui, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=6905763\" target=\"_blank\">Dependable Multicore Architectures at Nanoscale: the view from Europe<\/a>\u201d,&nbsp;<em>IEEE Design &amp; Test,&nbsp;<\/em>Vol. 32, Issue 2, April 2015, pp. 17-28.<\/li>\n\n\n\n<li>S. Neophytou and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/www.sciencedirect.com\/science\/article\/pii\/S0141933114000696\" target=\"_blank\">Multiple detection test generation with diversified fault partitioning paths<\/a>\u201d,&nbsp;<em>Microprocessors and Microsystems &#8211; Embedded Hardware Design (MICPRO)<\/em>,&nbsp;Vol. 38, No. 6, August 2014, pp. 585-597.<\/li>\n\n\n\n<li><em>S. Neophytou, C. Christou, <\/em>and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/www.eng.ucy.ac.cy\/mmichael\/JETTA_2012.pdf\" target=\"_blank\">A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits<\/a>\u201d,<em>&nbsp;Journal of Electronic Testing: Theory and Applications (JETTA),&nbsp;<\/em>Vol.28, No. 6, October 2012, pp. 843-856.<\/li>\n\n\n\n<li><em>C. Ttofis, T. Theocharides, <\/em>and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=5951809\" target=\"_blank\">FPGA-based Laboratory Assignments for NoC-based Manycore Systems<\/a>\u201d,<em>&nbsp;IEEE Transactions on Education,&nbsp;<\/em>Vol. 55, No. 3, May 2012, pp. 180-189.<\/li>\n\n\n\n<li><em>S. Neophytou<\/em> and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=5704232\" target=\"_blank\">Test Pattern Generation for Relaxed n-detect Test Sets<\/a>\u201d,&nbsp;<em>IEEE Transactions on Very Large Scale Integration (VLSI),&nbsp;<\/em>Vol. 20, No. 3, March 2012, pp. 410-423.<\/li>\n\n\n\n<li><em>R. Adapa<\/em>, S. Tragoudas, and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/dl.acm.org\/citation.cfm?id=1975361\" target=\"_blank\">Improved Diagnosis Using Enhanced Fault Dominance Relations<\/a>\u201d,&nbsp;<em>Integration, the VLSI Journal<\/em>, Vol. 44, No. 3, June 2011, pp. 217-228.<\/li>\n\n\n\n<li>C. Tofis, A. Papadopoulos, T. Theocharides, <strong>M. K. Michael<\/strong>, and D. Doumenis, &#8220;<a rel=\"noreferrer noopener\" href=\"https:\/\/jes-eurasipjournals.springeropen.com\/articles\/10.1155\/2011\/790265\" target=\"_blank\">An MPSoC-based QAM Modulation Architecture with Run-Time Load-Balancing<\/a>&#8220;,<em>&nbsp;EURASIP Journal of Embedded Systems,&nbsp;<\/em>Vol. 2011 (2011), Article ID 790265, 15 pages.<\/li>\n\n\n\n<li>T. Theocharides, <strong>M. K. Michael<\/strong>, M. Polycarpou, and A. Dingankar, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/jes-eurasipjournals.springeropen.com\/articles\/10.1155\/2010\/261434\" target=\"_blank\">Hardware-Enabled Dynamic Resource Allocation for Manycore Systems using Bidding-based System Feedback<\/a>\u201d,&nbsp;<em>EURASIP Journal on Embedded Systems,<\/em>&nbsp;Vol. 2010 (2010), Article ID 261434, 21 pages.<\/li>\n\n\n\n<li><em>S. Neophytou<\/em> and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=5342413\" target=\"_blank\">Test Set Generation With a Large Number of Unspecified Bits Using Static and Dynamic Techniques<\/a>\u201d,&nbsp;<em>IEEE Transactions on Computer,&nbsp;<\/em>Vol. 59, No. 3, March 2010, pp. 301-316.<\/li>\n\n\n\n<li><em>K. Christou<\/em>, <strong>M. K. Michael <\/strong>and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/www.eng.ucy.ac.cy\/mmichael\/JETTA_2008.pdf\" target=\"_blank\">On the use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation<\/a>\u201d,&nbsp;<em>Journal of Electronic Testing: Theory and Applications (JETTA),&nbsp;<\/em>Vol.24, No. 1 \u2013 3, June 2008, pp. 203-222.<\/li>\n\n\n\n<li>S. Neophytou, <strong>M. K. Michael<\/strong>, and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=4014553\" target=\"_blank\">Functions for Quality Transition Fault Tests and their Applications in Test Set Enhancement<\/a>\u201d,&nbsp;<em>IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems,&nbsp;<\/em>Vol. 25, No. 12, December 2006, pp. 3026-2035.<\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong> and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=1512190\" target=\"_blank\">Function-based Compact Test Pattern Generation for Path Delay Faults<\/a>\u201d,&nbsp;<em>IEEE Transactions on Very Large Scale Integration (VLSI)<\/em>, Vol. 13, No. 8, August 2005, pp. 996-1001.<\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong>, T. Haniotakis, and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=1302197\" target=\"_blank\">A Unified Framework for Generating Propagation Functions for Logic Errors and Events<\/a>\u201d,&nbsp;<em>IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems,<\/em>&nbsp;Vol. 23, No. 6, June 2004, pp. 980-986.<\/li>\n\n\n\n<li>S. Padmanaban, <strong>M. K. Michael<\/strong>, and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=1182075\" target=\"_blank\">Exact Path Delay Fault Coverage with Fundamental Zero-Suppressed BDD Operations<\/a>\u201d,&nbsp;<em>IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems,<\/em>&nbsp;Vol. 22, No. 3, March 2003, pp. 305-316.<\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong> and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"http:\/\/dl.acm.org\/citation.cfm?id=504916\" target=\"_blank\">ATPG Tools for Delay Faults at the Functional level<\/a>\u201d,&nbsp;<em>ACM Transactions On Design Automation of Electronic Systems (TODAES),&nbsp;<\/em>Vol. 7, Issue 1, January 2002, pp. 33-57.<\/li>\n<\/ul>\n<\/div><\/div>\n\n\n\n<p><strong>Refereed Conferences, Symposia &amp; Workshops with Proceedings<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>G. L. Stavrinides, <strong>M. K. Michael<\/strong>, T. Theocharides, \u201cOptimal Multi-Constrained Workflow Scheduling in the Edge-Cloud Continuum\u201d, <em>48<sup>th<\/sup> IEEE International Conference on Computers, Software, and Applications<\/em>, July 2024, Osaka, Japan, pp. 1-10.<\/li>\n\n\n\n<li>M. Asprou, C. Konstantinou and <strong>M. K. Michael<\/strong>, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/10408467\" target=\"_blank\" rel=\"noreferrer noopener\">Physics-Informed Neural Networks for Accelerating Power System State Estimation<\/a>\u201d, <em>IEEE PES Innovative Smart Grid Technologies Europe (ISGT-Europe)<\/em>, October 2023, Grenoble, France, pp. 1-5.<\/li>\n\n\n\n<li>, L. Hadjidemetriou, C. Laoudias and <strong>M. K. Michael<\/strong>, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/10224964\" target=\"_blank\" rel=\"noreferrer noopener\">Modelling and Analysing Security Threats Targeting Protective Relay Operations in Digital Substations<\/a>\u201d, <em>IEEE Cyber Security and Resilience Conference (CSR)<\/em>, July 2023, Venice, Italy, pp. 1-7.<\/li>\n\n\n\n<li><em>S. Datta<\/em>, P. Nicolaou and <strong>M. K. Michael<\/strong>, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/10189279\" target=\"_blank\" rel=\"noreferrer noopener\">Reputation-based User Vehicle Assignment in Intelligent and Connected Vehicle Platoons<\/a>\u201d, <em>IEEE International Conference on Omni-layer Intelligent Systems (COINS)<\/em>, August 2023, Berlin, Germany, pp. 1-7.<\/li>\n\n\n\n<li>N. Piperigkos, C. Anagnostopoulos, A. Lalos, S. Z. Zukhraf, Christos Laoudias, <strong>M. K. Michael<\/strong>, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/10185772\" target=\"_blank\" rel=\"noreferrer noopener\">Robust Cooperative Sparse Representation Solutions for Detecting and Mitigating Spoofing Attacks in Autonomous Vehicles<\/a>\u201d,<em> IEEE Mediterranean Conference on Control and Automation (MED2023)<\/em>, June 2023, Limassol, Cyprus, pp. 1-6.<\/li>\n\n\n\n<li>S. Filippou, A. Achilleos, S. Z. Zukhraf, C. Laoudias, K. Malialis, <strong>M. K. Michael<\/strong> and G. Ellinas, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/10200857\" target=\"_blank\" rel=\"noreferrer noopener\">Machine Learning Approach for Detecting GPS Location Spoofing Attacks in Autonomous Vehicles<\/a>\u201d, I<em>EEE Vehicular Technology Conference (VTC2023-Spring)<\/em>, June 2023, Florance, Italy, pp. 1-7.<\/li>\n\n\n\n<li>M. F. Elrawy, E. Tekki, L. Hadjidemetriou, C. Laoudias and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/10066371\" target=\"_blank\">Protection and Communication Model of Intelligent Electronic Devices to Investigate Security Threats<\/a>\u201d, <em>IEEE PES Innovative Smart Grid Technologies NA (ISGT-NA)<\/em>, January 2023, Washington-DC, USA, pp. 1-5.<\/li>\n\n\n\n<li>P. Nicolaou, Y. Sazeides and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9962363\" target=\"_blank\">INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling<\/a>\u201d, <em>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS2022)<\/em>, October 2022, Austin-Texas, USA, pp. 1-6.<\/li>\n\n\n\n<li>A. Kritikakou, P. Nikolaou, I. Rodriguez-Ferrandez, J. Paturel, L. Kosmidis, <strong>M. K. Michael<\/strong>, O. Sentieys and D. Steenari, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9897537\" target=\"_blank\">Functional and Timing Implications of Transient Faults in Critical Systems<\/a>\u201d, <em>IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)<\/em>, September 2022, Turin, Italy, pp. 1-10.<\/li>\n\n\n\n<li>K. Aslansefat, P. Nikolaou, M. Walker, M. N. Akram, I. Sorokos, J. Reich, P. Kolios, <strong>M. K. Michael<\/strong>, T. Theocharides, G. Ellinas, D. Schneider and Y. Papadopoulos, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/link.springer.com\/chapter\/10.1007\/978-3-031-15842-1_18\" target=\"_blank\">SafeDrones: Real-Time Reliability Evaluation of UAVs using Executable Digital Dependable Identities<\/a>\u201d, <em>International Symposium on Model-Based Safety and Assessment (IMBSA2022)<\/em>, September 2022, Munich, Germany, pp. 1-15.<\/li>\n\n\n\n<li><em>G. Tertytchny<\/em> and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9854937\" target=\"_blank\">Two-dimensional Dataset Reduction in Data-Driven Fault Detection for IoT-based Cyber Physical Systems<\/a>\u201d, <em>IEEE International Conference on Omni-layer Intelligent Systems (COINS)<\/em>, August 2022, Barcelona, Spain, pp. 1-6.<\/li>\n\n\n\n<li><em>M. F. Elrawy<\/em>, L. Hadjidemetriou, C. Laoudias and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9715626\" target=\"_blank\">Light-weight and Robust Network Intrusion Detection for Cyber-attacks in Digital Substations<\/a>\u201d, <em>IEEE PES Innovative Smart Grid Technologies Asia (ISGT Asia)<\/em>, December 2021, Brisbane, Australia, pp. 1-5.<\/li>\n\n\n\n<li><em>P. Corneliou<\/em>, P. Nikolaou, <strong>M. K Michael<\/strong>, T. Theocharides, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9568281\" target=\"_blank\">Fine-Grained Vulnerability Analysis of Resource Constrained Neural Inference Accelerators<\/a>\u201d, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October 2021, Athens, Greece, pp. 1-6.<\/li>\n\n\n\n<li><em>L. Stylianou<\/em>, L. Hadjidemetriou, M. Asprou, L. Zacharia and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9639905\" target=\"_blank\">A behavioral model to detect data manipulation attacks of synchrophasor measurements<\/a>\u201d, <em>IEEE PES Innovative Smart Grid Technologies Europe (ISGT Europe)<\/em>, October 2021, Espoo, Finland, pp. 1-6.<\/li>\n\n\n\n<li><em>S. Datta<\/em>, P. Nicolaou and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9564639\" target=\"_blank\">TrustPH: Trustworthy Platoon Head Selection considering Cognitive Biases to enhance Secure Platooning in Intelligent and Connected Vehicles<\/a>\u201d, <em>IEEE International Conference on Intelligent Transportation (ITSC)<\/em>, September 2021, Indianapolis, USA, pp. 1-8.<\/li>\n\n\n\n<li>R. Solomou, G. Savva, M. Mavrovouniotis, G. Ellinas, <strong>M. Michael<\/strong>, G. Spyrou and C. Pitris, \u201cExploring a disease network using random walks with bibliometric assessment to reveal potential disease-related pathways\u201d, <em>IEEE-EMBS International Conference on Biomedical and Health Informatics (BHI&#8217;21)<\/em>, July 2021, (extended abstract).<\/li>\n\n\n\n<li><em>S. Falas<\/em>, C. Konstantiou and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9283596\" target=\"_blank\">Physics-Informed Neural Networks for Securing Water Distribution Systems<\/a>\u201d, <em>38th IEEE International Conference on Computer Design (ICCD)<\/em>, October 2020, Hartford, CT, USA, pp. 37-40 <em>[invited referred paper].<\/em><\/li>\n\n\n\n<li>L. Hadjidemetriou, <em>G. Tertytchny<\/em>, H. Karbouj, C. Charalambous, <strong>M. K. Michael<\/strong>, M. Sazos and M. Maniatakos, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9248779\" target=\"_blank\">Demonstration of Man in the Middle Attack on a Feeder Power Factor Correction Unit<\/a>\u201d, <em>IEEE PES Innovative Smart Grid Technologies Europe (iSGT-Europe)<\/em>, October 2020, Hague, Belgium, pp. 126-130.<\/li>\n\n\n\n<li><em>G. Tertytchny<\/em>, H. Karbouj, L. Hadjidemetriou, C. Charalambous, <strong>M. K. Michael<\/strong>, M. Sazos and M. Maniatakos, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9311531\" target=\"_blank\">Demonstration of Man in the Middle Attack on a Commercial Photovoltaic Inverter Providing Ancillary Services<\/a>\u201d, <em>IEEE Cybersecurity of Power Electronics Systems (CyberPELS)<\/em>, co-located with <em>\u0399\u0395\u0395\u0395 Energy Conversion Congress &amp; Expo (ECCE)<\/em>, October 2020, Miami, FL, USA, pp. 1-7, doi: 10.1109\/CyberPELS49534.2020.9311531.<\/li>\n\n\n\n<li><em>S. Viktoros<\/em>,<strong> M. K. Michael<\/strong>, M. Polycarpou, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9192014\" target=\"_blank\">Compact Fault Dictionaries for Efficient Sensor Fault Diagnosis in IoT-enabled CPSs<\/a>\u201d, <em>IEEE SmartIoT Conference<\/em>, August 2020, Beijing, China, pp. 236-243.<\/li>\n\n\n\n<li><em>G.&nbsp; Tertytchny <\/em>and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9191393\" target=\"_blank\">Dataset Reduction Framework For Intelligent Fault Detection In IoT- based Cyber-Physical Systems Using Machine Learning Techniques<\/a>\u201d, <em>IEEE International Conference on Omni-layer Intelligent Systems (COINS)<\/em>, August 2020, Barcelona, Spain, pp. 1-6.<\/li>\n\n\n\n<li>K. Jaskie, S. Rao, W. Barnard, E. Kyriakides, I. Tofis, L. Hadjidemetriou, <strong>M. K. Michael<\/strong>, and A. Spanias, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9284359\" target=\"_blank\">IRES Program in Sensors and Machine Learning for Energy Systems<\/a>\u201d, IEEE International Conference on Information, Intelligence, Systems and Applications (IISA), July 2020, Athens, Greece, pp. 1-5 [recipient of Best Student Paper Award].<\/li>\n\n\n\n<li><em>A. Kouloumpris<\/em>, T. Theocharides and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/9154950\" target=\"_blank\">Cost-Effective Time-Redundancy based Optimal Task Allocation for the Edge-Hub-Cloud Systems<\/a>\u201d, <em>IEEE International Symposium on VLSI July 2020 (ISVLSI)<\/em>, Limassol, Cyprus, pp. 368-373.<\/li>\n\n\n\n<li><em>S. Falas<\/em>, C. Konstantinou, <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/8920348\" target=\"_blank\">A Hardware-based Framework for Secure Firmware Updates on Embedded Systems<\/a>\u201d, <em>IFIP\/IEEE International Conference on Very Large Scale Integration (VLSISoC)<\/em>, October 2019, Cusco, Perou, pp. 1-6.<\/li>\n\n\n\n<li><em>A. Kouloumpris<\/em>, <strong>M. K. Michael<\/strong>, T. Theocharides, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/8854422\" target=\"_blank\">Reliability-Aware Task Allocation Latency Optimization in Edge Computing<\/a>\u201d, <em>IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)<\/em>, July 2019, Rhodes, Greece, pp. 1-4.<\/li>\n\n\n\n<li><em>A. Kouloumpris<\/em>, T. Theocharides, <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/dl.acm.org\/doi\/10.1145\/3312614.3312643\" target=\"_blank\">Metis: Optimal Task Allocation Framework for the Edge\/Hub\/Cloud Paradigm<\/a>\u201d, <em>IEEE International Conference on Omni-Layer Intelligent Systems (COINS)<\/em>, May 2019, Crete, Greece, pp. 128-133.<\/li>\n\n\n\n<li><em>G. Tertytchny<\/em>, N. Nicolaou, <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/dl.acm.org\/doi\/10.1145\/3312614.3312642\" target=\"_blank\">Differentiating Attacks and Faults in Energy Aware Smart Home System using Supervised Machine Learning<\/a>\u201d, <em>IEEE International Conference on Omni-Layer Intelligent Systems (COINS)<\/em>, May 2019, Crete, Greece, pp. 122-127. <\/li>\n\n\n\n<li>P. M. Reddy, <em>S. Hadjitheophanous<\/em>, V. Soteriou, P. V. Gratz and <strong>M. K. Michael<\/strong>, &#8220;<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/8046205\" target=\"_blank\">Minimal exercise vector generation for reliability improvement<\/a>&#8220;,&nbsp;<em>Proc. of IEEE International On-Line Test Symposium (IOLTS)<\/em>, July 2017, Thessaloniki, Greece, pp. 113-119.<\/li>\n\n\n\n<li><em>S. Hadjitheophanous<\/em>, S. Neophytou and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/7519328\" target=\"_blank\">Utilizing shared memory multi-cores to speed-up the ATPG process<\/a>\u201d, <em>Proc. of 21<sup>st<\/sup>&nbsp;IEEE European Test Conference (ETS), May 2016<\/em>, pp. 1-6, Amsterdam \u2013 The Netherlands [acceptance rate ~20.5%].<\/li>\n\n\n\n<li><em>S. Hadjitheophanous<\/em>, <em>S. Neophytou <\/em>and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/7477313\" target=\"_blank\">Scalable Parallel Fault Simulation for Shared-Memory Multiprocessor Systems<\/a>\u201d, <em>Proc. of 34<sup>th<\/sup>&nbsp;IEEE VLSI Test Symposium (VTS)<\/em>, pp. 1-6, April 2016, Las Vegas \u2013 NV, USA.<\/li>\n\n\n\n<li><em>I. Chadjiminas, I. Savva<\/em>, C. Kyrkou,<strong> M. K. Michael<\/strong> and T. Theocharides, <a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/7459422\" target=\"_blank\">\u201cEmulation-Based Hierarchical Fault-Injection Framework for Coarse-to-Fine Vulnerability Analysis of HardwareAccelerated Approximate Algorithms<\/a>\u201d,&nbsp;<em>ACM\/IEEE Proc. of Design Automation and Test in Europe (DATE)<\/em>, March 2016, pp. 830-833, Dresden &#8211; Germany.<\/li>\n\n\n\n<li><em>I. Chadjiminas<\/em>, C. Kyrkou, C. Ttofis, T. Theocharides and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/7294003\" target=\"_blank\">In-Field Vulnerability Analysis of Hardware-Accelerated Computer Vision Applications<\/a>\u201d,&nbsp;<em>Proc. of 25<sup>th<\/sup>&nbsp;International Field Programmable Logic (FPL) Conference,&nbsp;<\/em>to appear, September 2015, London &#8211; UK.<\/li>\n\n\n\n<li><em>S. Skitsas<\/em>, C. A. Nicopoulos, and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/7229842\" target=\"_blank\">Toward Efficient Check-Pointing and Rollback Under On-Demand SBST in Chip Multi-Processors<\/a>\u201d,&nbsp;Proc. of IEEE International On-Line Test Symposium (IOLTS)<em>,<\/em>&nbsp;to appear, July 2015, Halkidiki &#8211; Greece.<\/li>\n\n\n\n<li><em>S. Neophytou<\/em> and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/7138741?reload=true\" target=\"_blank\">Tackling the Complexity of Exact Path Delay Fault Grading for Path Intensive Circuits<\/a>\u201d,<em>&nbsp;Proc. of 20<sup>th<\/sup>&nbsp;IEEE European Test Symposium (ETS)<\/em>, to appear, May 2015, Cluj-Napoca-Romania.<\/li>\n\n\n\n<li><em>S. Skitsas<\/em>, C. A. Nicopoulos, and <strong>M. K. Michael<\/strong>, \u201cExploring check-pointing and rollback recovery under selective SBST in Chip Multi- Processors\u201d,<em>&nbsp;Proc. of 4<sup>th<\/sup>&nbsp;MEDIAN Workshop<\/em>, March 2015, pp. 1- 4, Grenoble-France.<\/li>\n\n\n\n<li><em>S. Neophytou<\/em> and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/6974724\" target=\"_blank\">Optimal Variable Ordering in ZBDD-based Path Representations for Directed Acyclic Graphs<\/a>\u201d,&nbsp;<em>ACM\/IEEE Proc. of 32<sup>nd&nbsp;<\/sup>International Computer Design Conference (ICCD)<\/em>, October 2014, pp. 489-492, Seoul \u2013 Korea&nbsp;<em>[acceptance rate 34.7%]<\/em>.<\/li>\n\n\n\n<li><em>S. Skitsas<\/em>, C. A. Nicopoulos, and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/6962088\" target=\"_blank\">Exploration of System Availability During Software-Based Self-Testing in Many-core Systems Under Test Latency Constraints<\/a>\u201d,<em>&nbsp;IEEE Proc. of 27<sup>th&nbsp;<\/sup>Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS),&nbsp;<\/em>October 2014, pp. 1-7, Amsterdam \u2013 Netherlands&nbsp;<em>[acceptance rate 34%]<\/em>.<\/li>\n\n\n\n<li><em>S. Neophytou, S. Hadjitheophanous<\/em> and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/6727082\" target=\"_blank\">On the impact of fault list partitioning in parallel implementations for dynamic test compaction considering multicore systems<\/a>\u201d,&nbsp;<em>IEEE Proc. of International Design and Test Symposium (IDT),&nbsp;<\/em>December 2013, pp. 1-6, Marrakesh &#8211; Morocco.<\/li>\n\n\n\n<li>I. Voyiatzis, <em>S. Neophytou<\/em>, <strong>M. K. Michael<\/strong>, <em>S. Hadjitheophanous,&nbsp;<\/em>C. Sgouropoulou, and C. Efstathiou, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/6727147\" target=\"_blank\">Test set Embedding in Accumulator-generated sequences targeting Hard-To-detect faults<\/a>\u201d,&nbsp;<em>IEEE Proc. of International Design and Test Symposium (IDT),&nbsp;<\/em>December 2013, pp. 1-2, Marrakesh &#8211; Morocco.<\/li>\n\n\n\n<li><em>M. Skitsas<\/em>, C. A. Nicopoulos, and <strong>M. K. Michael<\/strong><em>,&nbsp;<\/em><a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/6653581?reload=true\" target=\"_blank\">\u201cDaemonGuard: O\/S-assisted selective software-based Self-Testing for multi-core systems<\/a>\u201d,<em>&nbsp;IEEE Proc. of Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS),&nbsp;<\/em>October 2013, pp. 45-51, New York City \u2013 USA.<\/li>\n\n\n\n<li>M. Maniatakos, <strong>M. K. Michael<\/strong>, and Y. Makris, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/6604050\" target=\"_blank\">Investigating the limits of AVF analysis in the presence of multiple bit errors<\/a>\u201d,&nbsp;<em>IEEE Proc. of International On-Line Test Symposium (IOLTS),<\/em>&nbsp;July 2013, pp. 49-54, Crete &#8211; Greece.<\/li>\n\n\n\n<li>M. Maniatakos, <strong>M. K. Michael<\/strong>, and Y. Makris, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/6513747\" target=\"_blank\">AVF-Driven Parity Optimization for MBU Protection of In-core Memory Arrays<\/a>\u201d,&nbsp;<em>ACM\/IEEE Proc. of Design Automation and Test in Europe (DATE),&nbsp;<\/em>March 2013<em>,<\/em>&nbsp;pp. 1480-1485, Grenoble \u2013 France&nbsp;<em>[acceptance rate 16.4%]<\/em>.<\/li>\n\n\n\n<li>M. Maniatakos, <strong>M. K. Michael<\/strong>, and Y. Makris, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/6401594\" target=\"_blank\">Vulnerability-Based Interleaving for Multi-Bit Upset (MBU) Protection in Modern Microprocessors<\/a>\u201d,&nbsp;<em>IEEE Proc. of International Test Conference (ITC),<\/em>&nbsp;November 2012, pp. 1-8, California &#8211; USA.<\/li>\n\n\n\n<li><strong>M. Skitsas<\/strong>, C. A. Nicopoulos, and <strong>M. K. Michael<\/strong><em>,&nbsp;<\/em>\u201cToward Selective Software-Based Self-Testing in Future Multi-core Microprocessors\u201d,&nbsp;<em>Proc. of 1<sup>st<\/sup>&nbsp;MEDIAN Workshop,&nbsp;<\/em>June 2012, pp. 71-75, Annecy &#8211; France.<\/li>\n\n\n\n<li><em>S. Neophytou, C. Christou<\/em>, and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/5957937\" target=\"_blank\">An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration<\/a>\u201d,&nbsp;<em>Proc. of IEEE European Test Symposium (ETS),&nbsp;<\/em>May 2011, pp. 141-146, Trondheim-Norway&nbsp;<em>[acceptance rate 29%]<\/em>.<\/li>\n\n\n\n<li>A. Papadopoulos, T. Theocharides and <strong>M.K. Michael<\/strong>, &#8220;<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/5937749\" target=\"_blank\">Towards optimal CMOS lifetime via unified reliability modeling and multi-objective optimization<\/a>&#8220;,&nbsp;<em>Proc. of IEEE International Symposium on Circuits And Systems (ISCAS),&nbsp;<\/em>May 2011, pp. 1-4, Brazil.<\/li>\n\n\n\n<li>C. Ttofis, A. Papadopoulos, T. Theocharides, <strong>M. K. Michael<\/strong> and D. Doumenis, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/5642606\" target=\"_blank\">A Reconfigurable MPSoC-based QAM Modulation Architecture<\/a>\u201d,&nbsp;<em>Proc. of 18<sup>th<\/sup>&nbsp;IEEE VLSI-SoC Conference (VLSI-SoC),&nbsp;<\/em>October 2010, pp. 137-142, Madrid \u2013 Spain&nbsp;<em>[acceptance rate ~40%]<\/em>.<\/li>\n\n\n\n<li><em>K. Christou<\/em>, <strong>M. K. Michael<\/strong>, <em>S. Neophytou<\/em>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/5469629\" target=\"_blank\">Identification of Critical Primitive Path Delay Faults without and Path Enumeration<\/a>\u201d,&nbsp;<em>Proc. of 28th IEEE VLSI Test Symposium (VTS)<\/em>, April 2010, pp. 9-14, Santa Cruz, CA &#8211; USA<em>.<\/em><\/li>\n\n\n\n<li><em>C. Ttofis<\/em>, C. Kyrkou, T. Theocharides, <strong>M.K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/5270845\" target=\"_blank\">FPGA-Based NoC-Driven Sequence of Lab Assignments for Manycore Systems<\/a>\u201d,&nbsp;<em>Proc. of IEEE Microelectronics Systems in Education Conference (MSE)<\/em>, July 2009, California &#8211; USA&nbsp;<em>[acceptance rate ~35%] [recipient of Best Paper Award].<\/em><\/li>\n\n\n\n<li><em>S. Neophytou<\/em>, <strong>M. K. Michael<\/strong>, <em>K. Christou<\/em>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/5372233\" target=\"_blank\">Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning<\/a>\u201d,&nbsp;<em>Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS),&nbsp;<\/em>October 2009, pp. 401-409, Chicago &#8211; USA.<\/li>\n\n\n\n<li>T. Theocharides, <strong>M. K. Michael<\/strong>, M. Polycarpou, A. Dingankar, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/dl.acm.org\/doi\/10.1145\/1531542.1531573\" target=\"_blank\">Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation<\/a>\u201d,&nbsp;<em>Proc. of ACM\/IEEE Great Lakes VLSI Symposium (GLSVLSI),&nbsp;<\/em>May 2009, pp. 121-124, Boston \u2013 USA&nbsp;<em>[long paper acceptance rate 16%]<\/em>.<\/li>\n\n\n\n<li>P. Bernardi, <em>K. Christou<\/em>, M. Grosso, <strong>M. K. Michael<\/strong>, E. Sanchez, M. Sonza Reorda, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/link.springer.com\/chapter\/10.1007\/978-3-540-78761-7_23\" target=\"_blank\">Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors<\/a>\u201d,&nbsp;<em>Proc. of Applications of Evolutionary Computing: EvoHOT, Lecture Notes in Computer Science,<\/em>&nbsp;Springer 2008, Volume 4974\/2008, 224-234, March 2008, Naples \u2013 Italy.<\/li>\n\n\n\n<li>T. Theocharides, <strong>M. K. Michael<\/strong>, M. Polycarpou, and A. Dingankar, \u201cDynamic System Level Optimization in MultiCore Architectures: The Example of Hardware Task Allocation\u201d,&nbsp;<em>6th HiPEAC Industrial Workshop<\/em>, November, 2008, pp. 1-6, Paris &#8211; France.<\/li>\n\n\n\n<li><em>K. Christou<\/em>, <strong>M. K. Michael<\/strong>, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/4511756\" target=\"_blank\" rel=\"noreferrer noopener\">A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm<\/a>\u201d,&nbsp;<em>Proc. of 26th IEE\u0395 VLSI Test Symposium (VTS)<\/em>, May 2008,pp. 389-394, San Diego, CA &#8211; USA.<\/li>\n\n\n\n<li><em>S. Neophytou<\/em> and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/4511720\" target=\"_blank\">On the Relaxation of N-detect Test Sets<\/a>\u201d,&nbsp;<em>Proc. of 26th IEEE VLSI Test Symposium (VTS)<\/em>, May 2008, pp. 187-192, San Diego-CA, USA.<\/li>\n\n\n\n<li>T. Theocharides, <strong>M. K. Michael<\/strong>, M. Polycarpou, and A. Dingankar, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/4556777\" target=\"_blank\">A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures\u201d<\/a>,&nbsp;<em>Proc. of IEEE Annual Symposium on VLSI (ISVLSI),<\/em>&nbsp;April 2008, pp. 99-104, Montpellier \u2013 France&nbsp;<em>[acceptance rate 30%]<\/em>.<\/li>\n\n\n\n<li><em>S. Neophytou<\/em> and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/4479845\" target=\"_blank\">Two New Methods for Accurate Test Set Relaxation via Test Set Replacement<\/a>\u201d,&nbsp;<em>Proc. of IEEE\/ACM International Symposium on Quality Electronic Design (ISQED),&nbsp;<\/em>March 2008, pp. 827-831, San Jose, CA &#8211; USA.<\/li>\n\n\n\n<li><em>S. Neophytou<\/em> and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/4358413\" target=\"_blank\">Hierarchical Fault Compatibility Identification for Compact Test Generation with a Large Number of Unspecified Bits<\/a>\u201d,&nbsp;<em>Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS),&nbsp;<\/em>September 2007, pp. 439-447, Rome &#8211; Italy.<\/li>\n\n\n\n<li><em>R. Adapa, <\/em>S. Tragoudas<em> <\/em>and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/4209916\" target=\"_blank\">Accelerating Diagnosis via Dominance Relations Between Sets of Faults<\/a>\u201d,<em>&nbsp;Proc. of IEEE VLSI Test Symposium (VTS)<\/em>, May 2007, pp. 219-224, Berkeley, CA &#8211; USA.<\/li>\n\n\n\n<li><em>K. Christou<\/em>, <strong>M. K. Michael <\/strong>and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/4030915\" target=\"_blank\">Implicit Critical PDF Test Generation with Maximal Test Efficiency<\/a>\u201d,&nbsp;<em>Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS),&nbsp;<\/em>October 2006, pp. 50-58, Washington-DC &#8211; USA.<\/li>\n\n\n\n<li><em>S. Neophytou<\/em>, <strong>M. K. Michael<\/strong> and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/1655514\" target=\"_blank\">Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding<\/a>\u201d,&nbsp;<em>Proc. of IEEE International On-Line Testing Symposium (IOLTS),&nbsp;<\/em>July 2006, pp. 43-48, Como &#8211; Italy.<\/li>\n\n\n\n<li><em>R. Adapa<\/em>, S. Tragoudas and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/1692710\" target=\"_blank\">Sub-Faults Identification for Collapsing in Diagnosis<\/a>\u201d,&nbsp;<em>Proc. of IEEE International Symposium on Circuits And Systems (ISCAS),<\/em>&nbsp;May 2006, pp. 815-818, Kos \u2013 Greece&nbsp;<em>[acceptance rate 35%]<\/em>.<\/li>\n\n\n\n<li><em>R. Adapa<\/em>, S. Tragoudas and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/1613176\" target=\"_blank\">Evaluation of Collapsing Methods for Fault Diagnosis<\/a>\u201d,&nbsp;<em>Proc. of IEEE\/ACM International Symposium on Quality Electronic Design (ISQED),<\/em>&nbsp;March 2006, pp. 439-444, San Jose, CA &#8211; USA&nbsp;<em>[acceptance rate 36.3%].<\/em><\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong>, <em>K. Christou<\/em>, and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/1524192\" target=\"_blank\">Towards finding path delay fault tests with high test efficiency using ZBDDs<\/a>\u201d,&nbsp;<em>IEEE\/ACM Proc. of International Conference on Computer Design (ICCD)<\/em>, Oct. 2005, pp. 464-467, San Jose, CA \u2013 USA&nbsp;<em>[acceptance rate 23%].<\/em><\/li>\n\n\n\n<li><em>S. Neophytou<\/em>, <strong>M. K. Michael<\/strong> and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/dl.acm.org\/doi\/10.1145\/1057661.1057706\" target=\"_blank\">Test set enhancement for quality transition faults using function-based methods<\/a>\u201d,&nbsp;<em>Proc. of IEEE\/ACM Great Lakes Symposium on VLSI (GLSVLSI)<\/em>, April 2005, pp. 182-187, Chicago, IL &#8211; USA&nbsp;<em>[long paper acceptance rate ~9%].<\/em><\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong>, S. Neophytou, and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/1410604\" target=\"_blank\">Functions for Quality Transition Fault Tests<\/a>\u201d,&nbsp;<em>Proc. of IEEE\/ACM International Symposium on Quality Electronic Design (ISQED),&nbsp;<\/em>March 2005, pp. 327-332, San Jose, CA &#8211; USA&nbsp;<em>[acceptance rate 37.3%] [Best Paper Award Nomination]<\/em>.<\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong> and S. Tragoudas, \u201cCompact Test Generation for Non-Robustly Testable PDFs\u201d,&nbsp;<em>Proc. of Circuits and Systems<\/em>, July 2004, pp. 1262-1269, Athens &#8211; Greece.41. <\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong> and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/1194769\" target=\"_blank\">Generation of Hazard Identification Functions<\/a>\u201d,<em>&nbsp;Proc. of IEEE\/ACM International Symposium on Quality Electronic Design (ISQED),&nbsp;<\/em>March 2003, pp. 511-516, San Jose, CA \u2013 USA&nbsp;<em>[acceptance rate 32.8%]<\/em>.<\/li>\n\n\n\n<li>S. Padmanaban, <strong>M. K. Michael<\/strong>, and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/966684\" target=\"_blank\">Exact Path Delay Grading with Fundamental BDD operations<\/a>\u201d,<em>&nbsp;Proc. of IEEE International Test Conference (ITC),<\/em>&nbsp;October 2001, pp. 642-651, Baltimore, MD &#8211; USA.<\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong> and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/915260\" target=\"_blank\">ATPG for Path Delay Faults without Path Enumeration<\/a>\u201d,<em>&nbsp;Proc. of IEEE\/ACM International Symposium on Quality Electronic Design (ISQED),<\/em>&nbsp;March 2001, pp. 384-389, San Jose, CA &#8211; USA.<\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong> and S. Tragoudas, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/836465\" target=\"_blank\">Functional-based ATPG for Path Delay Faults<\/a>\u201d,<em>&nbsp;Proc. of Southwest Symposium on Mixed-Signal Design<\/em>, April 2000, pp. 159-164, Arizona &#8211; USA&nbsp;<em>[invited paper]<\/em>.<\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong> and S. Tragoudas, \u201cA Method for Path Delay Fault ATPG in Embedded Cores\u201d,<em>&nbsp;Proc. of IEEE Workshop on Testing Embedded Core-based Systems<\/em>, April 1999, pp. 50-55, California &#8211; USA.<\/li>\n\n\n\n<li>S. Tragoudas and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/ieeexplore.ieee.org\/document\/757367\" target=\"_blank\">Functional ATPG for Delay Faults<\/a>\u201d,&nbsp;<em>Proc. of ACM\/IEEE Great Lakes Symposium on VLSI (GLSVLSI)<\/em>, March 1999, pp. 16-19, Ann Arbor, MI &#8211; USA.<\/li>\n\n\n\n<li>S. Tragoudas and <strong>M. K. Michael<\/strong>, \u201c<a rel=\"noreferrer noopener\" href=\"https:\/\/dl.acm.org\/doi\/abs\/10.1145\/504914.504916\" target=\"_blank\">ATPG tools for Delay Faults at the Functional Level<\/a>\u201d,<em>&nbsp;ACM\/IEEE Proc. of Design Automation and Test in Europe (DATE)<\/em>, March 1999, pp. 631-635, Munich &#8211; Germany.<\/li>\n<\/ul>\n\n\n\n<p><strong>Theses and Dissertations<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>M. K. Michael<\/strong>,&nbsp;<em>Test-based Timing Verification using Functional Techniques<\/em>, Ph.D. Dissertation, Electrical and Computer Engineering Department, Southern Illinois University at Carbondale, 2002.&nbsp;<em>[Nominated for Best Ph.D. Dissertation of the Year Award at SIU-C by College of Engineering].<\/em><strong><\/strong><\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong>,&nbsp;<em>Test Pattern Generation for Delay Faults at the Functional Level,<\/em>&nbsp;M.Sc. Thesis, Computer Science Department, Southern Illinois University at Carbondale, 1998.<\/li>\n<\/ul>\n\n\n\n<p><strong>Outreach Articles<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>M. K. Michael<\/strong>, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/1615279\" target=\"_blank\" rel=\"noreferrer noopener\">Encouraging Young Women Toward Engineering and Applied Sciences: ISIC\/MED Special Pro-conference Workshop<\/a>\u201d,Article appeared in<em> IEEE Control Systems Magazine<\/em>, April 2006.<\/li>\n\n\n\n<li><strong>M. K. Michael<\/strong>, \u201cTexnopleysi \u2013 The 1st National Robotics Competition in Cyprus\u201d, Article appeared in <em>Phileleftheros and Simerini <\/em>newspapers, as well as in <em>Koinotita<\/em>, University of Cyprus Publication, June 2006.<\/li>\n<\/ul>\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Book Chapters: Refereed Archival Journal Articles: Refereed Conferences, Symposia &amp; Workshops with Proceedings Theses and Dissertations Outreach Articles<\/p>\n","protected":false},"author":1,"featured_media":11,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-39","page","type-page","status-publish","has-post-thumbnail","hentry"],"_links":{"self":[{"href":"https:\/\/www.kios.ucy.ac.cy\/mmichael\/index.php\/wp-json\/wp\/v2\/pages\/39","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.kios.ucy.ac.cy\/mmichael\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.kios.ucy.ac.cy\/mmichael\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.kios.ucy.ac.cy\/mmichael\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.kios.ucy.ac.cy\/mmichael\/index.php\/wp-json\/wp\/v2\/comments?post=39"}],"version-history":[{"count":135,"href":"https:\/\/www.kios.ucy.ac.cy\/mmichael\/index.php\/wp-json\/wp\/v2\/pages\/39\/revisions"}],"predecessor-version":[{"id":361,"href":"https:\/\/www.kios.ucy.ac.cy\/mmichael\/index.php\/wp-json\/wp\/v2\/pages\/39\/revisions\/361"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.kios.ucy.ac.cy\/mmichael\/index.php\/wp-json\/wp\/v2\/media\/11"}],"wp:attachment":[{"href":"https:\/\/www.kios.ucy.ac.cy\/mmichael\/index.php\/wp-json\/wp\/v2\/media?parent=39"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}